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PRELIMINARY
W217
Spread AwareTM, Eight Output Zero Delay Buffer
Features
* Spread AwareTM--designed to work with SSFTG reference signals * Eight LVCMOS/LVTTL outputs * 5.0V power supply * Available in 24-pin SOIC (300 mil) package
Key Specifications
Operating Voltage: ................................................ 5.0V10% Operating Range: .......................... 30 MHz < fOUT < 35 MHz Cycle-to-Cycle Jitter: ................................................<200 ps Output to Output Skew: ............................................<250 ps PLL Lock Time:............................................................<25 ps
Block Diagram
FBIN REF
Pin Configurations
PLL MUX Q0 Q1 Q2
REF VDD NC NC VDD VDD Q0 Q1
Q5 Q6 Q7
1 2 3 4 5
24 23 22 21 20
GND BYPASS NC GND VDD Q7 Q6 GND Q5 Q4 VDD FBIN
BYPASS Q3 Q4
W217
6 7 8 9 10 11 12
19 18 17 16 15 14 13
GND Q2 Q3 VDD
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 November 29, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name REF FBIN Pin No. 1 13 Pin Type I I Pin Description Reference Input: Output signals Q0:7 will be synchronized to this signal.
W217
Feedback Input: This input must be fed by one of the outputs to ensure proper functionality. If the trace between FBIN and output is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Integrated Series Resistor Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. Power Connections: Connect to 5.0V. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connections: Connect to common system ground plane. PLL Bypass: Tie to GND (LOW,0) for normal operation, when brought to V DD (HIGH, 1) the onboard PLL is bypassed, eliminating the `zero delay' feature. No Connect: Leave these pins floating for normal operation.
Q0:7
7, 8, 10,11, 15, 16, 18, 19 2, 5, 6, 12, 14, 20 9, 17, 21, 24 23 3, 4, 22
O
VDD GND BYPASS NC
P G I I
Overview
The W217 is a PLL-based clock driver designed for use in RAID systems. External feedback allows users to lay out their systems so that the devices being driven by the outputs are accurately synchronized to the clock signal provided as a reference to the W217.
1
REF VDD NC NC VDD VDD Q0 Q1 GND Q2 Q3 VDD
GND B YP AS S NC GND VDD Q7 Q6 GND Q5 Q4 VDD F BIN
24 23 22 21 20 19 18 17 16 15 14 13
VDD
FB
10F
0.1F
2 3 4 5
0.1F 0.1F
0.1F
VDD
6 7
VDD
8 9
0.1F
10 11 12
0.1F
VDD
Figure 1. Schematic
2
PRELIMINARY
Spread AwareTM
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
W217
External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked.
AC Test Load
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going high at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below.
Output pin
4" trace
30pf
Figure 2. Test Load Schematic
3
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating Parameter VDD, VIN TSTG TB TA PD Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Power Dissipation
W217
only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Exceeding maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 0.75 Unit V C C C W
DC Electrical Characteristics: TA = 0C to +70C, VDD = 5.0V10%
Parameter IDD VIL VIH VOL VOH IIL IIH CIN ROut Description Supply Current 5.0V Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current - REF/FB Input Low Current - BYPASS Input High Current - REF/FB BYPASS Input Capacitance Output Driver Impedance VIN = V DD 10 55 IOL = 46 mA IOH = -16 mA VIN = 0V 2.4 500 200 500 200 2.0 0.4 Condition Unloaded, 33 MHz Min. Typ. 110 Max. 130 0.8 Unit mA V V V V A A A pF
AC Electrical Characteristics: TA = 0C to +70C, VDD = 5.0V10%
Parameter fOUT tR tF tICLKR tICLKF tPE tSK tD tLOCK tJC Description Output Frequency Output Rise Time Output Fall Time Input Clock Rise Time CLK to FBIN Skew Duty Cycle
[3] [2] [1]
Condition 30-pF load 0.8V to 2.0V, 30-pF load 2.0V to 0.8V, 30-pF load
Min. 30
Typ. 1.0 1.0
Max. 35 1.5 1.5 4.5 4.5
Unit MHz ns ns ns ns ps ps % s ps
Input Clock Fall Time[1] Measured at 1.5V All outputs loaded equally 30-pF load Power supply stable -250 -250 45 0 0 50 7 Output to output Skew PLL lock time Jitter, Cycle-to-cycle
250 250 55 25 200
Notes: 1. Longer input rise and fall time will degrade skew and jitter performance. 2. Skew is measured at 1.5V on rising edges. 3. Duty Cycle measured at 1.5V.
Ordering Information
Ordering Code W217 Document #38-00828 Package Name X Package Type 24-pin TSSOP
4
PRELIMINARY
Package Diagram
24-Pin Small Outline Integrated Circuit Package (SOIC)
W217
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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